Physical Design Blog Series

Welcome!

This 10-part blog series covers the complete VLSI physical design flow. From floorplanning to signoff - each post is self-contained and written in simple language. Start anywhere or read them all!

Part 1

Introduction to Physical Design

Overview of PD flow, inputs/outputs, and key concepts

Part 2

Floorplanning

Die size, core area, macro placement, pin assignment

Part 3

Power Planning

Power grid, rings, straps, and IR drop basics

Part 4

Placement

Global placement, legalization, optimization

Part 5

Clock Tree Synthesis (CTS)

Clock distribution, skew, latency, buffers

Part 6

Routing

Global routing, detail routing, DRC fixing

Part 7

Timing Closure

Setup/hold fixing, optimization techniques

Part 8

Physical Verification

DRC, LVS, antenna checks, ERC

Part 9

Power Analysis

IR drop, EM analysis, power optimization

Part 10

Signoff & Tapeout

Final checks, GDSII generation, tapeout checklist