┌─────────────────────────────────────────────────────────────┐ │ SIGNOFF CHECKS │ ├─────────────────────────────────────────────────────────────┤ │ ✓ Timing Signoff (STA) │ │ ✓ Physical Verification (DRC/LVS) │ │ ✓ Power Signoff (IR/EM) │ │ ✓ Formal Verification │ │ ✓ Signal Integrity │ │ ✓ Layout vs Layout (if ECO) │ ├─────────────────────────────────────────────────────────────┤ │ ↓ │ │ ALL CHECKS MUST PASS! │ │ ↓ │ │ TAPEOUT │ │ (Send GDSII to foundry) │ └─────────────────────────────────────────────────────────────┘

1. Extract parasitics (SPEF)
   StarRC, QRC, or similar

2. Run STA across all corners
   PrimeTime, Tempus

3. Check setup and hold
   All views must be clean

4. Check for:
   - Max transition violations
   - Max capacitance violations
   - Max fanout violations

RTL Layout Netlist (Verilog) (post-route) │ │ └──────┬───────────────┘ │ ┌──────▼──────┐ │ Formal │ │ Equivalence │ │ Check │ └──────┬──────┘ │ ▼ EQUIVALENT? YES ✓ or NO ✗

# Formality example
read_sverilog -r rtl.v          # Reference (golden)
read_verilog -i layout.v        # Implementation
verify                          # Compare

# Must show: PASS - Designs are equivalent

# Export GDSII
streamOut final_design.gds \
  -mapFile layer.map \
  -libName my_lib \
  -structureName top \
  -units 1000

# Verify GDSII
gdsView final_design.gds   # Visual check

┌─────────────────────────────────────────────────────────────┐ │ TAPEOUT CHECKLIST │ ├─────────────────────────────────────────────────────────────┤ │ │ │ TIMING: │ │ □ Setup timing clean (all corners) │ │ □ Hold timing clean (all corners) │ │ □ Max transition clean │ │ □ Max capacitance clean │ │ □ Clock domain crossings verified │ │ │ │ PHYSICAL: │ │ □ DRC clean │ │ □ LVS clean │ │ □ Antenna clean │ │ □ Density within limits │ │ □ Metal fill added │ │ │ │ POWER: │ │ □ Static IR drop < 5% │ │ □ Dynamic IR drop < 10% │ │ □ EM analysis clean │ │ □ Power consumption within budget │ │ │ │ VERIFICATION: │ │ □ Formal equivalence check passed │ │ □ All corners/modes verified │ │ □ GDSII generated correctly │ │ │ └─────────────────────────────────────────────────────────────┘

GDSII sent to Foundry │ ▼ ┌───────────────┐ │ Mask Creation │ (Foundry makes masks) └───────┬───────┘ │ ▼ ┌───────────────┐ │ Fabrication │ (Chip manufactured) └───────┬───────┘ │ ▼ ┌───────────────┐ │ Packaging │ (Die put in package) └───────┬───────┘ │ ▼ ┌───────────────┐ │ Testing │ (Chips tested) └───────┬───────┘ │ ▼ Working Chips!