Part 3 of 10
Power Planning
Building a robust power distribution network
By Praveen Kumar Vagala
Why Power Planning Matters
Power must reach every cell with minimal voltage drop (IR drop).
VDD at pad = 1.0V
│
│ Wire resistance
▼
VDD at cell = 0.95V ← 5% drop = 50mV!
If IR drop too high:
• Cells run slower (setup violations)
• May cause functional failures
• Reliability issues
Power Network Structure
┌─────────────────────────────────────────────────────────────────┐
│ │
│ ═══════════════════════════════════════════════════ ← Ring │
│ ║ ║ (VDD) │
│ ║ ═══════════════════════════════════════════ ║ │
│ ║ ║ ║ ║ ← Ring │
│ ║ ║ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ║ ║ (VSS) │
│ ║ ║ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ║ ║ │
│ ║ ║ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ║ ║ ← Straps │
│ ║ ║ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ║ ║ (vertical)│
│ ║ ║ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ┃ ║ ║ │
│ ║ ═════════════════════════════════════════ ║ ← Straps │
│ ║ ║ (horiz) │
│ ═════════════════════════════════════════════════ │
│ │
│ ──VDD────────────────────────────────────────── ← Rails │
│ ──VSS────────────────────────────────────────── (in rows) │
│ ──VDD────────────────────────────────────────── │
│ │
└─────────────────────────────────────────────────────────────────┘
Power Network Components
| Component | Layer | Purpose |
|---|
| Power Ring | Top metals | Distribute power around chip |
| Power Straps | Upper metals | Carry power across chip |
| Power Rails | M1 | Supply power to standard cells |
| Vias | Between layers | Connect different metal layers |
Power Ring
Forms a ring around the core area on thick top metals.
# Create power ring (Innovus)
addRing \
-nets {VDD VSS} \
-type core_rings \
-layer {top M9 bottom M9 left M8 right M8} \
-width 5 \
-spacing 2 \
-offset 3
Power Straps
Vertical and horizontal metal lines that carry power from ring to cells.
# Add power straps (Innovus)
addStripe \
-nets {VDD VSS} \
-layer M6 \
-direction vertical \
-width 2 \
-spacing 1 \
-set_to_set_distance 50 \
-start_from left \
-start_offset 10
# Horizontal straps
addStripe \
-nets {VDD VSS} \
-layer M7 \
-direction horizontal \
-width 2 \
-spacing 1 \
-set_to_set_distance 50
Via Stacking
Power Pad
│
════════╪════════ M9 (Ring)
│
────────┼──────── M8
│
════════╪════════ M7 (Strap)
│
────────┼──────── M6
│
════════╪════════ M5 (Strap)
│
... │ ...
│
────────┴──────── M1 (Rail)
│
Cells
Via stack connects all layers!
Standard Cell Rails
Horizontal M1 rails in each row supply cells directly.
Row 2: ──VDD─────────────────────────────────
┌─────┐ ┌─────┐ ┌───────┐ ┌─────┐
│ INV │ │ BUF │ │ AND │ │ MUX │
└─────┘ └─────┘ └───────┘ └─────┘
──VSS─────────────────────────────────
Row 1: ──VDD─────────────────────────────────
┌─────┐ ┌───────┐ ┌─────┐
│ OR │ │ NOR │ │ XOR │
└─────┘ └───────┘ └─────┘
──VSS─────────────────────────────────
IR Drop
IR Drop = Current × Resistance
VDD = 1.0V
│
R1=10mΩ │
▼
┌───────┴───────┐
│ 0.99V │
│ │
R2 │ R3 │
▼ ▼
0.97V 0.98V
Cells far from power pads see lower voltage!
IR Drop Guidelines
- Static IR drop: < 5% of VDD (typical target)
- Dynamic IR drop: < 10% during switching
- Increase strap width/count to reduce IR drop
Electromigration (EM)
High current density causes metal atoms to move, eventually breaking wires.
EM Limits:
Each metal layer has maximum current density (mA/um).
Power straps must be wide enough to stay under limits!
Current density = Total current / Wire cross-section
If current = 100mA and wire width = 2um, thickness = 0.5um:
Density = 100mA / (2 × 0.5) = 100 mA/um²
Check against library EM limits!
Macro Power Connections
Macros have their own power pins that must connect to the grid.
Power Strap (M6)
│
═════╪═════════════════════
│
┌────┴────────────────────┐
│ VDD pin │
│ │
│ MACRO │
│ (SRAM) │
│ │
│ VSS pin │
└────┬────────────────────┘
│
═════╪═════════════════════
│
Power Strap (M6)
Power Mesh Density
| Block Type | Power Mesh | Reason |
|---|
| High-speed logic | Dense mesh | High switching current |
| Memory blocks | Dense mesh | Many cells switching |
| Low-power logic | Sparse mesh | Lower current |
| Clock buffers | Dense mesh | High switching |
Commands Summary (Innovus)
# Power planning flow
globalNetConnect VDD -type pgpin -pin VDD -all
globalNetConnect VSS -type pgpin -pin VSS -all
# Create ring
addRing -nets {VDD VSS} -type core_rings ...
# Create straps
addStripe -nets {VDD VSS} -layer M6 ...
# Special route (connect rails to straps)
sroute -connect corePin
# Verify
verifyConnectivity -nets {VDD VSS}
analyzeIRDrop
Summary
| Component | Key Point |
|---|
| Power Ring | Around core on top metals |
| Power Straps | Carry power across chip |
| Power Rails | M1 rails to cells |
| IR Drop | Keep < 5% of VDD |
| EM | Stay under current limits |