Part 2 of 10
Floorplanning
Defining chip size and organizing major blocks
By Praveen Kumar Vagala
What is Floorplanning?
Floorplanning is the first step - defining the chip's physical dimensions and placing major components.
┌────────────────────────────────────────────────────────────────┐
│ I/O Pads (Top) │
├────────┬───────────────────────────────────────────────┬───────┤
│ │ │ │
│ I/O │ CORE AREA │ I/O │
│ Pads │ ┌──────────┐ ┌──────────┐ │ Pads │
│(Left) │ │ MACRO │ │ MACRO │ │(Right)│
│ │ │ (SRAM) │ │ (PLL) │ │ │
│ │ └──────────┘ └──────────┘ │ │
│ │ │ │
│ │ Standard Cell Placement Area │ │
│ │ │ │
├────────┴───────────────────────────────────────────────┴───────┤
│ I/O Pads (Bottom) │
└────────────────────────────────────────────────────────────────┘
Key Terms
| Term | Description |
|---|
| Die Area | Total chip area (includes I/O pads) |
| Core Area | Area available for logic (inside I/O ring) |
| Utilization | % of core area filled with cells |
| Aspect Ratio | Width / Height of core |
| Macro | Large pre-designed block (SRAM, PLL, etc.) |
Die Size Calculation
Core Area = Total Cell Area / Target Utilization
Example:
Total cell area = 1,000,000 um²
Target utilization = 70%
Core Area = 1,000,000 / 0.70 = 1,428,571 um²
If aspect ratio = 1:
Width = Height = √1,428,571 = 1,195 um
Die Area = Core Area + I/O Pad Area + Margins
Utilization Guidelines:
60-70%: Standard (room for optimization)
70-80%: Tight (challenging timing closure)
80%+: Very tight (may not close timing)
Macro Placement
Macros must be placed first - they're fixed during placement.
Macro Placement Guidelines
Good Placement: Bad Placement:
┌────────────────────┐ ┌────────────────────┐
│ ┌────┐ ┌────┐│ │ ┌────┐ │
│ │SRAM│ │SRAM││ │ │SRAM│ ┌────┐ │
│ └────┘ └────┘│ │ ┌──┴────┴─┤SRAM│ │
│ │ │ │ └────┘ │
│ Standard Cells │ │ │ Congested! │
│ │ │ └──────────────────│
└────────────────────┘ └────────────────────┘
Macros on edges, Macros blocking
clear routing channels routing paths
Macro Placement Rules
- Place macros along chip edges
- Keep macros away from core center
- Align macro pins to routing grid
- Leave space (channels) between macros
- Consider data flow - place related macros close
Macro Halos and Blockages
┌─────────────────┐
│ Halo │
│ ┌───────────┐ │
│ │ │ │
│ │ MACRO │ │
│ │ │ │
│ └───────────┘ │
│ │
└─────────────────┘
Halo: Keep-out zone around macro
(no cells placed here)
# Innovus command example
createPlaceBlockage -type hard -box {x1 y1 x2 y2}
createPlaceBlockage -type soft -box {x1 y1 x2 y2} # Soft = can be violated
# Halo around macro
createPlaceBlockage -inst SRAM1 -haloDistance {5 5 5 5}
I/O Planning
Signal Pads Power Pads
↓ ↓
┌────┬────┬────┬────┬────┬────┬────┬────┐
│ IO │ IO │ IO │VDD │VSS │ IO │ IO │ IO │ ← Pad Ring
├────┴────┴────┴────┴────┴────┴────┴────┤
│ │
│ CORE │
│ │
└────────────────────────────────────────┘
Pin Placement Considerations
- Group related signals together
- Place pins near their internal connections
- Power pins distributed evenly
- Consider signal integrity (separate sensitive signals)
Floorplan Checks
| Check | What to Verify |
|---|
| Utilization | 60-70% target range |
| Macro overlap | No overlapping macros |
| Routing channels | Enough space between macros |
| Power grid space | Room for power straps |
| Timing paths | Critical macros placed optimally |
Commands Example (Innovus)
# Initialize design
read_verilog design.v
read_lef tech.lef cell.lef
read_sdc design.sdc
# Create floorplan
floorPlan -site core -r 1.0 0.7 10 10 10 10
# -site: row type
# -r 1.0: aspect ratio
# 0.7: utilization
# 10 10 10 10: margins (left bottom right top)
# Place macros
placeInstance SRAM_inst 100 200 R0
# Create blockages
createPlaceBlockage -box {0 0 50 1000} -type hard
# Verify floorplan
checkFPlan
Summary
| Concept | Key Point |
|---|
| Floorplan | Define chip size and major blocks |
| Utilization | 60-70% typical target |
| Macros | Place on edges, leave channels |
| I/O Pads | Ring around core |
| Halos | Keep-out zones around macros |