Part 1 of 10
Introduction to Physical Design
What is PD and why does it matter?
By Praveen Kumar Vagala
What is Physical Design?
Physical Design (PD) is the process of converting a gate-level netlist into a physical layout that can be manufactured as a chip.
FRONT-END BACK-END (Physical Design)
┌────────────┐ ┌─────────────────────────────────────┐
│ RTL │ │ Netlist → Floorplan → Placement │
│ Design │──Synthesis──►│ → CTS → Routing → Signoff │
│ (Verilog) │ │ → GDSII │
└────────────┘ └─────────────────────────────────────┘
Physical Design!
Why Physical Design Matters
- Timing - Wire delays can exceed gate delays in advanced nodes
- Power - 50%+ of chip power is in interconnect
- Area - Smaller die = lower cost
- Manufacturability - Must follow foundry rules
PD Flow Overview
┌─────────────────────────────────────────────────────────────────┐
│ Physical Design Flow │
├─────────────────────────────────────────────────────────────────┤
│ │
│ 1. FLOORPLANNING │
│ └── Die size, IO placement, macro placement │
│ ↓ │
│ 2. POWER PLANNING │
│ └── Power rings, straps, rails │
│ ↓ │
│ 3. PLACEMENT │
│ └── Place standard cells │
│ ↓ │
│ 4. CLOCK TREE SYNTHESIS (CTS) │
│ └── Build balanced clock network │
│ ↓ │
│ 5. ROUTING │
│ └── Connect all signals │
│ ↓ │
│ 6. SIGNOFF │
│ └── Timing, DRC, LVS, IR drop → GDSII │
│ │
└─────────────────────────────────────────────────────────────────┘
Inputs to Physical Design
| Input | Description | From |
|---|
| Gate-level Netlist | .v file with gates and connections | Synthesis |
| SDC (Constraints) | Timing constraints, clocks | Design team |
| LEF/Tech LEF | Cell abstracts, metal layers | Foundry/Library |
| Liberty (.lib) | Timing, power info for cells | Library vendor |
| DEF (optional) | Pre-existing placement info | Previous run |
Outputs from Physical Design
| Output | Description | Goes To |
|---|
| GDSII | Final layout for manufacturing | Foundry |
| DEF | Design Exchange Format | Verification |
| Netlist (post-route) | Final netlist with buffers | LVS, STA |
| SPEF/SDF | Parasitics, delays | Timing signoff |
Key File Formats
LEF (Library Exchange Format)
MACRO INV_X1
CLASS CORE ;
SIZE 0.4 BY 1.2 ;
PIN A
DIRECTION INPUT ;
PORT
LAYER M1 ;
RECT 0.0 0.4 0.1 0.8 ;
END
END A
PIN Y
DIRECTION OUTPUT ;
PORT
LAYER M1 ;
RECT 0.3 0.4 0.4 0.8 ;
END
END Y
END INV_X1
DEF (Design Exchange Format)
DESIGN my_chip ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1000000 1000000 ) ;
COMPONENTS 100 ;
- U1 INV_X1 + PLACED ( 10000 20000 ) N ;
- U2 AND2_X1 + PLACED ( 10400 20000 ) N ;
END COMPONENTS
NETS 50 ;
- net1 ( U1 Y ) ( U2 A ) ;
END NETS
Standard Cell Basics
Standard cells are pre-designed logic gates with fixed height.
┌─────────────────────────────────────────────────┐
│ VDD Rail │
├─────────────────────────────────────────────────┤
│ │
│ ┌─────┐ ┌─────┐ ┌───────┐ ┌─────┐ ┌─────┐ │
│ │ INV │ │ INV │ │ AND │ │ OR │ │ BUF │ │
│ │ │ │ │ │ │ │ │ │ │ │ ← Fixed height
│ └─────┘ └─────┘ └───────┘ └─────┘ └─────┘ │ (cell row)
│ │
├─────────────────────────────────────────────────┤
│ VSS Rail │
└─────────────────────────────────────────────────┘
←───────────── Variable widths ───────────────────→
Metal Layers
Modern chips have 10+ metal layers for routing:
Top View: Side View:
M5 ════════ ─────── M5 (thick, power)
─────── M4
M4 ║ ║ ║ ║ ─────── M3
─────── M2
M3 ════════ ─────── M1
─────── Poly
M2 ║ ║ ║ ║ ═══════ Substrate
M1 ════════
Horizontal: M1, M3, M5 (odd layers)
Vertical: M2, M4, M6 (even layers)
PD Tools
| Vendor | Tool | Purpose |
|---|
| Cadence | Innovus | Place & Route |
| Synopsys | ICC2 | Place & Route |
| Synopsys | PrimeTime | Timing signoff |
| Cadence | Tempus | Timing signoff |
| Synopsys | StarRC | Parasitic extraction |
| Cadence | Pegasus/PVS | DRC/LVS |
Summary
| Concept | Key Point |
|---|
| Physical Design | Netlist → GDSII |
| Main Steps | Floorplan → Place → CTS → Route |
| Key Input | Netlist, SDC, LEF, Liberty |
| Key Output | GDSII (for fabrication) |