Part 4 of 10
Placement
Positioning standard cells for optimal timing and routability
By Praveen Kumar Vagala
What is Placement?
Placement determines where each standard cell sits in the chip.
Before Placement: After Placement:
A bunch of cells ┌─────────────────────────┐
floating around │ INV BUF AND MUX OR XOR │
○ ○ ○ │ NOR NAND BUF FF FF │
○ ○ ○ │ AND AND OR MUX BUF │
○ ○ ○ │ FF INV XOR AND NOR │
└─────────────────────────┘
Cells in rows, legal positions
Placement Stages
┌─────────────────────────────────────────────────────────────┐
│ 1. GLOBAL PLACEMENT │
│ • Rough placement of all cells │
│ • Cells may overlap │
│ • Minimize total wire length │
├─────────────────────────────────────────────────────────────┤
│ 2. LEGALIZATION │
│ • Remove overlaps │
│ • Snap cells to legal row positions │
│ • Align to placement grid │
├─────────────────────────────────────────────────────────────┤
│ 3. DETAILED PLACEMENT │
│ • Fine-tune positions │
│ • Optimize for timing │
│ • Reduce local congestion │
└─────────────────────────────────────────────────────────────┘
Placement Objectives
| Objective | Why |
|---|
| Minimize wire length | Shorter wires = faster signals, less power |
| Meet timing | Critical paths get priority |
| Reduce congestion | Ensure routing is possible |
| Balance density | Even utilization across chip |
Cell Rows
Standard cells are placed in horizontal rows.
Row 4: ──VDD──────────────────────────────
┌───┐┌───┐┌─────┐┌───┐┌───┐┌───┐
│ ││ ││ ││ ││ ││ │
└───┘└───┘└─────┘└───┘└───┘└───┘
──VSS──────────────────────────────
Row 3: ──VDD──────────────────────────────
┌───┐┌───────┐┌───┐┌───┐┌───┐
│ ││ ││ ││ ││ │
└───┘└───────┘└───┘└───┘└───┘
──VSS──────────────────────────────
Cells have fixed height, variable width
Rows alternate orientation (N, FS, N, FS...)
VDD/VSS rails shared between adjacent rows
Placement Constraints
Placement Blockages
# Hard blockage - no cells allowed
createPlaceBlockage -type hard -box {100 100 200 200}
# Soft blockage - cells allowed if needed
createPlaceBlockage -type soft -box {300 100 400 200}
# Partial blockage - reduced density
createPlaceBlockage -type partial -box {500 100 600 200} -density 50
Cell Groups and Regions
# Group related cells together
createInstGroup critical_group -cells {U1 U2 U3 U4}
# Create region and assign group
createRegion region1 100 100 300 300
assignInstGroup region1 critical_group
# Fence - cells MUST be in region
createFence fence1 -box {100 100 300 300}
addInstToFence fence1 {U1 U2 U3}
Timing-Driven Placement
Critical paths get priority during placement.
Timing-driven placement:
┌───┐ Short wire! ┌───┐
│FF1│ ═══════════════════► │FF2│
└───┘ Critical path └───┘
┌───┐ ┌───┐
│FF3│ ─────────────────────────►│FF4│
└───┘ Non-critical (longer) └───┘
Tools analyze timing and place critical cells closer.
Congestion
Too many wires in one area = routing problems.
Low Congestion: High Congestion:
┌───────────────────┐ ┌───────────────────┐
│ │ │ ╔═╦═╦═╦═╗ │
│ ─── ─── ─── │ │ ║ ║ ║ ║ ║ │
│ ─── ─── │ │ ╠═╬═╬═╬═╣ │
│ ─── ─── ─── │ │ ║ ║ ║ ║ ║ │
│ │ │ ╚═╩═╩═╩═╝ │
└───────────────────┘ └───────────────────┘
Good: Wires spread out Bad: Too many wires!
May not route!
Congestion Fixes
- Reduce utilization in congested areas
- Add placement blockages
- Spread cells using density screens
- Use congestion-driven placement mode
Optimization During Placement
| Optimization | What It Does |
|---|
| Buffer insertion | Add buffers for long wires |
| Gate sizing | Upsize cells on critical paths |
| Cell swapping | Replace cells with better variants |
| Cloning | Duplicate high-fanout drivers |
Scan Chain Reordering
DFT scan chains should follow placement order to reduce wire length.
Before reorder: After reorder:
1 ──────────┐ 1 ─► 2 ─► 3
│ │
3 ◄─────────┤ 4 ◄─ 5 ◄─┘
│ │
2 ◄─────────┘ 6 ◄─┘
Long wires crossing! Short local connections
Placement Commands (Innovus)
# Set placement mode
setPlaceMode -timingDriven true
setPlaceMode -congestionEffort high
# Run placement
place_design
# Or step by step:
place_opt_design -global # Global placement
place_opt_design -detail # Detailed placement
# Check placement
checkPlace
reportCongestion
# Optimize after placement
optDesign -preCTS
Placement Quality Metrics
| Metric | Good Value |
|---|
| Total WNS (setup) | Positive or small negative |
| Total TNS | Close to 0 |
| Max congestion | < 1.0 (no overflow) |
| Utilization | Within 5% of target |
| HPWL | Minimize (wire length) |
Summary
| Stage | Key Point |
|---|
| Global | Initial rough placement |
| Legalization | Remove overlaps, align to rows |
| Detailed | Fine-tune for timing |
| Timing-driven | Critical paths placed closer |
| Congestion | Avoid routing hotspots |