Part 5 of 10
Clock Tree Synthesis (CTS)
Distributing the clock with minimal skew
By Praveen Kumar Vagala
Why CTS Matters
Clock must reach all flip-flops at nearly the same time.
Without CTS: With CTS:
CLK ─────┬───────► FF1 CLK ──┬── BUF ──┬── BUF ──► FF1
│ │ │
└───────► FF2 │ └── BUF ──► FF2
│ │
└► FF3 └── BUF ──┬── BUF ──► FF3
│
Clock reaches FFs at └── BUF ──► FF4
different times!
Balanced tree - clock arrives together!
Key CTS Terms
| Term | Definition |
|---|
| Clock Source | Origin of clock (PLL, input pin) |
| Clock Sink | Destination (flip-flop clock pins) |
| Insertion Delay | Time from source to sink |
| Skew | Difference in arrival times between sinks |
| Latency | Average delay from source to sinks |
Clock Skew
CLK Source
│
┌─────┴─────┐
│ │
BUF BUF
│ │
┌───┴───┐ ┌───┴───┐
│ │ │ │
FF1 FF2 FF3 FF4
Arrival times:
FF1: 1.2ns
FF2: 1.3ns
FF3: 1.1ns
FF4: 1.25ns
Skew = max - min = 1.3 - 1.1 = 0.2ns
Why Skew Matters
Hold time requirement:
Tcq + Tcomb > Thold + Tskew
If skew is large → hold violations!
Setup time:
Tcq + Tcomb + Tsetup < Tperiod + Tskew
Positive skew helps setup (data has more time)
Clock Tree Topologies
H-Tree
CLK
│
┌───────┴───────┐
│ │
┌───┴───┐ ┌───┴───┐
│ │ │ │
┌──┴──┐ ┌──┴──┐ ┌──┴──┐ ┌──┴──┐
│ │ │ │ │ │ │ │
FF FF FF FF FF FF FF FF
H-Tree: Symmetric, equal path lengths
Good for uniform sink distribution
Fishbone
CLK ═════════════════════════════════════
│ │ │ │ │ │
▼ ▼ ▼ ▼ ▼ ▼
FF FF FF FF FF FF
Fishbone: Central spine with branches
Good for row-based designs
CTS Flow
┌───────────────────────────────────────┐
│ 1. Define Clock Tree Specification │
│ • Target skew, max latency │
│ • Buffer types to use │
│ • Routing layers │
├───────────────────────────────────────┤
│ 2. Build Clock Tree │
│ • Insert buffers/inverters │
│ • Balance delays │
├───────────────────────────────────────┤
│ 3. Route Clock Nets │
│ • Use preferred clock layers │
│ • Non-default rules (NDR) │
├───────────────────────────────────────┤
│ 4. Optimize │
│ • Fix skew violations │
│ • Balance insertion delay │
└───────────────────────────────────────┘
Clock Tree Buffers
Special cells designed for clock trees:
| Property | Clock Buffer | Regular Buffer |
|---|
| Drive strength | High | Various |
| Balanced rise/fall | Yes | Not always |
| Low jitter | Yes | Not optimized |
CTS Constraints
# Clock tree specification (Innovus)
create_ccopt_clock_tree_spec
set_ccopt_property -clock_tree clk \
-target_skew 50ps \
-target_max_trans 100ps \
-buffer_cells {CLKBUF_X8 CLKBUF_X16}
# Clock routing rules
set_ccopt_property -routing_rule clk_routing_rule
-preferred_layers {M4 M5}
-width 0.2
-spacing 0.2
Non-Default Rules (NDR)
Clock nets use wider wires and more spacing for reliability.
Regular routing: Clock routing (NDR):
═══ ═══ ═══ ════════
─── ─── ───
═══ ═══ ═══ ═══
Minimum width/space 2x width, 2x space
Lower resistance,
Less coupling
Useful Skew
Sometimes intentional skew helps timing!
Problem: Setup violation on path A→B
CLK─┬─► FF_A ────(long path)────► FF_B
│
Without skew: Data arrives late!
Solution: Add latency to FF_B clock (useful skew)
CLK─┬─────────► FF_A ───────────┐
│ │
└── BUF ─► FF_B ◄───────────┘
│
Clock arrives later,
data has more time!
CTS Commands (Innovus)
# Pre-CTS checks
checkClockTree
# Run CTS
ccopt_design
# Or step by step:
ccopt_design -cts # Build tree
ccopt_design -hold # Fix hold violations
# Reports
report_ccopt_clock_trees
report_ccopt_skew_groups
# Check quality
reportClockTree -summary
Post-CTS Optimization
After CTS, clock is fixed. Now optimize data paths:
# Post-CTS optimization
optDesign -postCTS
# Fix hold violations
optDesign -postCTS -hold
# Incremental optimization
optDesign -postCTS -incr
CTS Quality Metrics
| Metric | Good Target |
|---|
| Clock skew | < 100ps (advanced nodes) |
| Max insertion delay | Depends on clock period |
| Buffer count | Minimize (power) |
| Hold violations | 0 (after fixing) |
Summary
| Concept | Key Point |
|---|
| Skew | Difference in clock arrival times |
| Latency | Delay from source to sinks |
| CTS goal | Minimize skew, balance tree |
| NDR | Wider wires for clock nets |
| Useful skew | Intentional skew for timing |