Before Routing: After Routing: ┌───┐ ┌───┐ ┌───┐═════════┌───┐ │ A │ → │ B │ │ A │ │ B │ └─┬─┘ └───┘ └─┬─┘ ║ └─┬─┘ │ │ ║ │ │ ┌───┐ ╠══════╝ │ └──→ │ C │ ║ │ └───┘ ╚═════════════╝ │ via │ ┌─┴─┐ ┌─┴─┐ │ C │ │ C │ └───┘ └───┘ Logical connections Physical metal wires

┌─────────────────────────────────────────────────────────────┐ │ 1. GLOBAL ROUTING (Track Assignment) │ │ • Divide chip into regions (GCells) │ │ • Plan rough paths through regions │ │ • No actual wires yet │ ├─────────────────────────────────────────────────────────────┤ │ 2. DETAIL ROUTING │ │ • Create actual metal geometries │ │ • Follow DRC rules (width, spacing) │ │ • Insert vias at layer changes │ ├─────────────────────────────────────────────────────────────┤ │ 3. SEARCH & REPAIR (DRC Fixing) │ │ • Find and fix DRC violations │ │ • Reroute problematic areas │ └─────────────────────────────────────────────────────────────┘

Usage Direction M10-M12 ═══ Power (thick) Horizontal M7-M9 ═══ Semi-global Mixed M5-M6 ║║║ Signal routing Alternating M3-M4 ═══ Signal routing Alternating M1-M2 ║║║ Local connections Alternating Odd layers: Horizontal (M1, M3, M5...) Even layers: Vertical (M2, M4, M6...) (Convention varies by foundry)

Track 1 Track 2 Track 3 Track 4 │ │ │ │ ───┼────────┼────────┼────────┼─── M3 │ │ │ │ │ ════╪════════╪════ │ Wire on M3 │ │ │ │ ───┼────────┼────────┼────────┼─── │ │ │ │ ║ ║ ║ ║ M2 (vertical) │ │ │ │ │ │ Via │ │ ───┼────────┼────╳───┼────────┼─── M1 │ │ │ │ Wires follow tracks (routing grid) Vias connect layers

Cross-section: Top view: ══════════ M3 ┌──────────┐ ┃┃┃ │ ┌──────┐ │ ══════════ M2 │ │ Via │ │ M2 ┃┃┃ │ │Array │ │ ══════════ M1 │ └──────┘ │ └──────────┘ Via stack connects M1 multiple layers

GCell overflow: ┌───────────────────────────────────────┐ │ 4 tracks │ 4 tracks │ │ available │ available │ │ │ │ │ 6 nets need │ 2 nets need │ │ to cross! │ to cross │ │ │ │ │ OVERFLOW! │ OK │ └───────────────────────────────────────┘ Solutions: - Spread cells in placement - Use more routing layers - Increase GCell density

During manufacturing, plasma etches metal. Long wire collects charge → damages thin gate oxide. ════════════════════════════════► Long wire │ ┌──┴──┐ │Gate │ ← Damaged! └─────┘ Fix: Add antenna diodes or break wire with layer changes.

Victim net: ────────────────────────► ↑ coupling ↑ Aggressor: ════════════════════════► When aggressor switches: - Victim signal gets noise (glitch) - Victim timing changes (delay) Fix: Space wires, use shielding, different layers

# Set routing options
setRouteMode -earlyGlobalHonorMsvRouteConstraint false
setRouteMode -timing true

# Global route
route_global

# Detail route
route_detail

# Or combined:
routeDesign

# Fix DRC violations
routeDesign -wireOpt

# ECO routing (incremental)
ecoRoute

# Check routing
verifyConnectivity
verify_drc

# Post-route optimization
optDesign -postRoute

# Fix timing with routing
setOptMode -postRouteAllowOverlaps false
optDesign -postRoute -hold

# Fix SI (crosstalk)
optDesign -postRoute -si