Part 7 of 10

Timing Closure

Meeting timing requirements across all corners

By Praveen Kumar Vagala

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What is Timing Closure?

Timing closure means all timing requirements are met - no setup or hold violations.

Timing Report Startpoint: reg_A/Q Endpoint: reg_B/D Path Type: max (setup) Point Delay Path ───────────────────────────────────────── clock clk (rise) 0.000 0.000 reg_A/CK 0.500 0.500 (clock latency) reg_A/Q 0.150 0.650 (Tcq) U1/Y (AND2) 0.080 0.730 U2/Y (OR2) 0.095 0.825 U3/Y (BUF) 0.060 0.885 reg_B/D (setup) 0.050 0.935 ───────────────────────────────────────── Data Arrival Time 0.935 Clock clk (rise) 1.000 1.000 (period) reg_B/CK 0.480 1.480 (clock latency) library setup time -0.050 1.430 ───────────────────────────────────────── Data Required Time 1.430 Slack = 1.430 - 0.935 = 0.495ns (MET) ✓

Key Timing Terms

Term	Definition
WNS	Worst Negative Slack - worst path
TNS	Total Negative Slack - sum of all violations
Slack	Required time - Arrival time (positive = good)
Setup	Data must be stable before clock edge
Hold	Data must be stable after clock edge

PVT Corners

Design must work across all Process, Voltage, Temperature conditions.

Corner	Process	Voltage	Temp	Used For
Worst Setup (SS)	Slow	Low	High	Setup analysis
Best Hold (FF)	Fast	High	Low	Hold analysis
Typical (TT)	Typical	Nominal	25°C	Reference

Setup Violations

Data arrives TOO LATE (after setup window).

Problem: Path is too slow, data misses clock edge reg_A ──► Long path (slow) ──► reg_B │ Data arrives late! Solutions: 1. Upsize cells (faster) 2. Add buffers (reduce load) 3. Reduce wire length (better placement) 4. Use parallel paths 5. Lower clock frequency

Fixing Setup Violations

# Upsize a cell
ecoChangeCell -inst U1 -cell AND2_X4  # X1 → X4

# Add buffer to reduce fanout
ecoAddRepeater -net slow_net -cell BUF_X4

# Optimize automatically
optDesign -postRoute -setup

Hold Violations

Data arrives TOO FAST (before hold window ends).

Problem: Path is too fast, data changes too quickly reg_A ──► Short path (fast) ──► reg_B │ Data changes before hold ends! Solutions: 1. Add delay buffers 2. Downsize cells (slower) 3. Increase wire length (rarely) 4. CANNOT change clock frequency!

Fixing Hold Violations

# Add delay buffer
ecoAddRepeater -net fast_net -cell DELAY_X1

# Optimize automatically
optDesign -postRoute -hold

# Check hold after fixing
timeDesign -postRoute -hold

Optimization Techniques

Technique	For Setup	For Hold
Cell sizing	Upsize ↑	Downsize ↓
Buffer insertion	Reduce load	Add delay
Vt swapping	Use LVT	Use HVT
Wire optimization	Shorten wires	Longer wires (rare)
Logic restructuring	Parallel paths	N/A

Useful Skew

Intentionally delay clock to help setup timing.

Before useful skew: CLK─┬─► FF_A ───(slow path)───► FF_B SETUP VIOLATION! │ │ └─────────────────────────────┘ CLK arrives same time After useful skew: CLK─┬───────────► FF_A ───────────┐ │ │ └── BUF ─► FF_B ◄──────────────┘ │ CLK delayed at FF_B More time for data!

Multi-Corner Multi-Mode (MCMM)

Analyze timing across multiple scenarios simultaneously.

# Define corners
create_timing_condition tc_slow -library slow.lib
create_timing_condition tc_fast -library fast.lib

# Define modes
create_mode func_mode -sdc func.sdc
create_mode test_mode -sdc test.sdc

# Create analysis views
create_analysis_view view_slow_func \
  -timing_condition tc_slow \
  -mode func_mode

# Run MCMM analysis
timeDesign -postRoute

Timing ECO (Engineering Change Order)

Small fixes after routing is complete.

# Manual cell swap
ecoChangeCell -inst U1 -cell BUF_X8

# Add buffer
ecoAddRepeater -term U2/A -cell BUF_X2

# Remove cell
ecoDeleteRepeater -inst BUF1

# Legalize after ECO
ecoPlace

# Route ECO changes
ecoRoute

Timing Closure Flow

┌─────────────────────────────────────────────────────────────┐ │ 1. Run initial timing analysis │ │ timeDesign -postRoute -reportOnly │ ├─────────────────────────────────────────────────────────────┤ │ 2. Fix setup violations first │ │ optDesign -postRoute -setup │ ├─────────────────────────────────────────────────────────────┤ │ 3. Fix hold violations │ │ optDesign -postRoute -hold │ ├─────────────────────────────────────────────────────────────┤ │ 4. Re-check timing │ │ timeDesign -postRoute │ ├─────────────────────────────────────────────────────────────┤ │ 5. Iterate until clean │ │ WNS = 0, TNS = 0, No hold violations │ └─────────────────────────────────────────────────────────────┘

Timing Reports

# Summary report
report_timing -summary

# Worst paths
report_timing -nworst 10

# Hold report
report_timing -delay_type min

# Check specific path
report_timing -from reg_A/Q -to reg_B/D

# All violating paths
report_timing -max_slack 0

Summary

Concept	Key Point
Setup	Data arrives before clock
Hold	Data stable after clock
WNS	Worst single violation
TNS	Total of all violations
Corners	SS for setup, FF for hold

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