Part 8 of 10

Physical Verification

DRC, LVS, and other checks before tapeout

By Praveen Kumar Vagala

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What is Physical Verification?

Physical verification ensures the layout can be manufactured and matches the design intent.

┌─────────────────────────────────────────────────────────────┐ │ Physical Verification Checks │ ├─────────────────────────────────────────────────────────────┤ │ │ │ DRC (Design Rule Check) │ │ └── Can the foundry manufacture this? │ │ │ │ LVS (Layout vs Schematic) │ │ └── Does layout match the netlist? │ │ │ │ ERC (Electrical Rule Check) │ │ └── Any floating nodes? Shorts to power? │ │ │ │ Antenna Check │ │ └── Will long wires damage gates? │ │ │ │ DFM (Design for Manufacturing) │ │ └── Will the design yield well? │ │ │ └─────────────────────────────────────────────────────────────┘

DRC (Design Rule Check)

Foundry provides rules that must be followed for manufacturing.

Common DRC Rules

Rule	Description	Example
Minimum width	Wire can't be too thin	M1 width ≥ 0.1μm
Minimum spacing	Wires must be apart	M1 space ≥ 0.1μm
Enclosure	Metal around via	Via1 enc by M1 ≥ 0.05μm
Area	Minimum metal area	M1 area ≥ 0.01μm²
Density	Metal fill percentage	M1 density 20-80%

DRC violations: Minimum Width: Minimum Spacing: ══ ═══ ═══ Bad! Too thin Bad! Too close ═════ ═══ ═══ Good! Good! Via Enclosure: ┌──┐ ┌────────┐ │▣▣│ Bad! │ ▣▣ │ Good! └──┘ └────────┘ Via touches edge Metal surrounds via

LVS (Layout vs Schematic)

Verifies the layout matches the original netlist.

Netlist (Source) Layout (GDSII) ┌───┐ ┌───┐ ┌───┐═════┌───┐ │ A │──────│ B │ │ A │ │ B │ └───┘ └───┘ └───┘ └───┘ │ │ └────────┌───┐ └══════┌───┐ │ C │ │ C │ └───┘ └───┘ LVS Tool compares them. ✓ Same devices? ✓ Same connections? ✓ Same nets?

LVS Errors

Error	Meaning	Common Cause
Short	Extra connection	Routing touches wrong net
Open	Missing connection	Broken route, missing via
Device mismatch	Wrong cell type	Wrong cell placed
Port mismatch	Pin not connected	Missing pin connection

ERC (Electrical Rule Check)

Checks for electrical problems.

Floating nodes - Unconnected inputs
Shorts - VDD shorted to VSS
Fanout violations - Too many loads
Level shifter missing - Voltage domain crossing

Antenna Check

Long metal wires can damage gates during manufacturing.

During plasma etching: Long metal antenna ═══════════════════════════════► │ ┌──┴──┐ │Gate │ ← Charge damages gate! └─────┘ Antenna Ratio = Metal Area / Gate Area If ratio > limit → violation!

Antenna Fixes

Add antenna diode (drains charge)
Layer hopping (break wire with via)
Reroute on different layer

# Check antenna
verifyProcessAntenna

# Auto-fix antenna
setAnalysisMode -checkAntennaEffects true
routeDesign -fix_antenna

Metal Fill

Add dummy metal to meet density rules.

Before fill: After fill: ═══ ═══ ═══ ▪ ▪ ▪ ═══ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ═══════════════ ═══════════════ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ═══ ▪ ▪ ═══ ▪ ▪ ▪ Uneven density Balanced density Fill metal is not connected to signals.

# Add metal fill
addFiller -cell FILL* -prefix FILL

# Or density-based fill
setFillerMode -density 0.5
addFiller

Verification Flow

┌─────────────────────────────────────────────────────────────┐ │ 1. Export GDSII from P&R tool │ ├─────────────────────────────────────────────────────────────┤ │ 2. Run DRC (Calibre, PVS, ICV) │ │ • Fix all violations │ ├─────────────────────────────────────────────────────────────┤ │ 3. Run LVS │ │ • Compare layout to netlist │ │ • Fix shorts/opens │ ├─────────────────────────────────────────────────────────────┤ │ 4. Run Antenna check │ │ • Insert diodes if needed │ ├─────────────────────────────────────────────────────────────┤ │ 5. Add metal fill │ │ • Meet density requirements │ ├─────────────────────────────────────────────────────────────┤ │ 6. Final DRC/LVS clean check │ │ • Must be 0 errors! │ └─────────────────────────────────────────────────────────────┘

Verification Tools

Vendor	Tool	Purpose
Mentor	Calibre	DRC, LVS, DFM
Cadence	PVS/Pegasus	DRC, LVS
Synopsys	ICV	DRC, LVS

Common Commands

# In P&R tool (Innovus)
verify_drc
verify_connectivity -type all

# Export for signoff tools
streamOut design.gds -mapFile tech.map

# Calibre (command line)
calibre -drc -hier design.drc
calibre -lvs design.lvs

Summary

Check	What It Verifies
DRC	Manufacturing rules
LVS	Layout matches netlist
ERC	Electrical connectivity
Antenna	Long wire damage
Metal Fill	Density requirements

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