Design for Testability - From Basics to Production
This 11-part blog series covers everything you need to start working in DFT. From Linux basics and Verilog to ATPG, BIST, and real tool flows. Each post builds on the previous one - start from the beginning or jump to any topic.
Master the command line for EDA tools. Navigation, file operations, grep, and GVIM basics.
Combinational vs sequential logic, setup/hold time, metastability, and FSMs.
Write DFT-friendly RTL. Blocking vs non-blocking, common mistakes, scan flip-flop structure.
Why DFT matters. Controllability, observability, and the ASIC design flow.
The backbone of structural testing. Scan FFs, shift-capture-shift, DRC rules.
Automatic test pattern generation. Fault models, coverage, and ATPG algorithms.
Reduce test time 100x. Decompressor, compactor, and compression trade-offs.
Catch timing defects. LOC vs LOS, transition faults, at-speed patterns.
Built-In Self-Test. MBIST for memories, LBIST for logic, LFSR and MISR.
IEEE 1149.1 standard. TAP controller, boundary scan, daisy chaining.
Real tool commands. DFT Compiler, TetraMAX, coverage reports, debugging.
Master digital logic, combinational & sequential circuits, FSMs, timing analysis, and RTL coding.
10 Part SeriesFrom netlist to GDSII - floorplanning, placement, CTS, routing, timing closure, and signoff.
10 Part SeriesExplore all blog series - Design Verification and more VLSI topics.
Complete Collection