Part 10 of 11
JTAG (IEEE 1149.1)
The universal debug and test interface
By Praveen Kumar Vagala
What is JTAG?
JTAG = Joint Test Action Group
A standard 5-wire interface for testing and debugging chips. Found on nearly every modern chip.
┌─────────────────────────────────────────┐
│ │
│ TDI ─────────────────────────────────►│
│ (Test Data In) │
│ │
│ TDO ◄─────────────────────────────────│
│ (Test Data Out) │
│ │
│ TCK ─────────────────────────────────►│
│ (Test Clock) │
│ │
│ TMS ─────────────────────────────────►│
│ (Test Mode Select) │
│ │
│ TRST ────────────────────────────────►│
│ (Test Reset - optional) │
│ │
└─────────────────────────────────────────┘
The 5 JTAG Signals
| Signal | Direction | Purpose |
|---|
| TDI | Input | Serial data into chip |
| TDO | Output | Serial data out of chip |
| TCK | Input | Test clock |
| TMS | Input | Controls TAP state machine |
| TRST | Input | Async reset (optional) |
Key insight: Only 5 pins to access the entire chip!
TAP Controller
TAP = Test Access Port
A state machine that controls JTAG operations.
TMS=1 (stay in reset)
┌─────────────┐
│ │
▼ │
┌──────────┐ │
┌──────►│Test-Logic│────────┘
│ │ Reset │
│ └────┬─────┘
│ │ TMS=0
│ ▼
│ ┌──────────┐
│ ┌───│Run-Test/ │◄──┐
│ │ │ Idle │ │ TMS=0
│ │ └────┬─────┘───┘
│ │ │ TMS=1
│ │ ▼
│ │ ┌──────────┐ ┌──────────┐
│ │ │Select-DR │──TMS=1─►│Select-IR │
│ │ │ Scan │ │ Scan │
│ │ └────┬─────┘ └────┬─────┘
│ │ │ TMS=0 │ TMS=0
│ │ ▼ ▼
│ │ (DR Path) (IR Path)
│ │ │ │
└───┴─────────┴───────────────────┘
(from Update-DR/IR)
Main Paths
- DR Path: Access Data Registers (scan chains, bypass, ID)
- IR Path: Load Instructions (tell TAP what to do)
JTAG Instructions
Common instructions loaded via IR path:
| Instruction | Opcode | Purpose |
|---|
| BYPASS | All 1s | Pass data through (1-bit register) |
| EXTEST | Varies | Test external connections |
| SAMPLE | Varies | Sample I/O pins |
| INTEST | Varies | Test internal logic |
| IDCODE | Varies | Read chip ID |
| USERCODE | Varies | User-defined code |
JTAG Scan Operations
1. Load Instruction
1. Go to Shift-IR state
2. Shift instruction into IR
3. Go to Update-IR
4. Instruction takes effect
2. Shift Data
1. Go to Shift-DR state
2. Shift data in/out through selected register
3. Go to Update-DR
4. New data takes effect
Boundary Scan
JTAG's original purpose: test connections between chips on a board.
Chip A Chip B
┌──────────┐ ┌──────────┐
│ ○─────│────────────────│─────○ │
│ ○─────│────────────────│─────○ │
│ ○─────│────────────────│─────○ │
└──────────┘ └──────────┘
↑ ↑
Boundary Boundary
Scan Cells Scan Cells
Boundary Scan Cell
┌─────────────────────┐
From Core ──────►│ │──────► To Pin
│ Boundary Cell │
From Pin ──────►│ │──────► To Core
└──────────┬──────────┘
│
┌──────────┴──────────┐
Shift Update Mode
(TDI/TDO) Reg Control
Each I/O pin has a boundary scan cell that can:
- Capture pin value (sample)
- Drive pin value (force)
- Pass through normally (transparent)
Daisy Chaining
Multiple chips share one JTAG interface:
TDI ──►[Chip1]──►[Chip2]──►[Chip3]──► TDO
↑ ↑ ↑
└─────────┴─────────┴── TCK, TMS (shared)
Addressing Specific Chip
To access Chip2 only:
1. Put Chip1 in BYPASS (1-bit delay)
2. Put Chip2 in target mode (EXTEST, etc.)
3. Put Chip3 in BYPASS (1-bit delay)
4. Shift data: [Chip1 bypass][Chip2 data][Chip3 bypass]
JTAG Use Cases
1. Board-Level Testing
- Test solder joints
- Find opens/shorts
- Verify connections
2. Chip Debugging
- Access internal scan chains
- Read/write internal registers
- Control debug modes
3. Programming
- Flash/FPGA programming
- Fuse programming
- Security features
4. In-System Test
- Production testing
- Field diagnostics
- Firmware updates
JTAG Tools
| Tool | Purpose |
|---|
| BSDL file | Describes chip's JTAG interface |
| SVF file | Portable test vectors |
| JTAG debugger | Hardware interface (SEGGER, etc.) |
| OpenOCD | Open-source JTAG software |
Summary
| Concept | Key Point |
|---|
| JTAG | 5-wire standard test interface |
| TAP | State machine controller |
| TDI/TDO | Serial data path |
| Boundary Scan | Test board connections |
| Instructions | BYPASS, EXTEST, IDCODE, etc. |
| Daisy chain | Multiple chips, one interface |