Part 9 of 11
BIST - Built-In Self-Test
The chip that tests itself
By Praveen Kumar Vagala
What is BIST?
BIST = Built-In Self-Test
Test logic embedded inside the chip. No expensive external tester needed.
Without BIST: With BIST:
ββββββββββ ββββββββ βββββββββββββββββββββ
βExternalββββββΊβ Chip β β Chip β
βTester βββββββ β β ββββββββββββββββ β
ββββββββββ ββββββββ β β BIST Engine β β
$$$$$$ β ββββββββββββββββ β
Expensive! β Self-contained! β
βββββββββββββββββββββ
Two Types of BIST
| Type | Tests | Use Case |
| MBIST | Embedded memories (SRAM) | Standard for all memories |
| LBIST | Random logic | High-reliability applications |
MBIST - Memory BIST
Architecture
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β MBIST Controller β
β β
β ββββββββββββββββ β
β β Address βββββββββββββββββ β
β β Generator β β β
β ββββββββββββββββ β β
β βΌ β
β ββββββββββββββββ ββββββββββββ β
β β Data ββββββββββΊβ β β
β β Generator β β SRAM β β
β ββββββββββββββββ β ββββββ β
β ββββββββββββ β β
β ββββββββββββββββ β β
β β Expected β β β
β β Data βββββββββ β β
β ββββββββββββββββ β β β
β βΌ βΌ β
β ββββββββββββββββββββββββββββ β
β β Comparator β β
β βββββββββββββ¬βββββββββββββββ β
β β β
β PASS/FAIL β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
How It Works
- Address Generator: Cycles through all memory locations
- Data Generator: Creates test patterns (0s, 1s, checkerboard)
- Write to SRAM: Store test data
- Read from SRAM: Retrieve stored data
- Compare: Match expected vs actual
- Report: PASS if all match, FAIL otherwise
March Algorithm
Industry-standard memory test pattern.
March C- Algorithm
Step 1: β(w0) Write 0 to all locations, ascending
Step 2: β(r0,w1) Read 0, write 1, ascending
Step 3: β(r1,w0) Read 1, write 0, ascending
Step 4: β(r0,w1) Read 0, write 1, descending
Step 5: β(r1,w0) Read 1, write 0, descending
Step 6: β(r0) Read 0, descending
Notation:
β = Ascending address order
β = Descending address order
w0 = Write 0
r1 = Read and expect 1
What March Catches
| Fault Type | Description |
| Stuck-at | Cell always 0 or 1 |
| Transition | Cell can't change |
| Coupling | One cell affects another |
| Address decoder | Wrong cell accessed |
| Read/Write logic | Data corruption |
LBIST - Logic BIST
Tests random logic using pseudo-random patterns.
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β β
β ββββββββββ ββββββββββββββββ ββββββββββ β
β β LFSR βββββββΊβ βββββββΊβ MISR β β
β β(Patternβ β Circuit β β(Signtr)β β
β β Gen) β β Under Test β β β β
β ββββββββββ ββββββββββββββββ ββββββ¬ββββ β
β β β
β βΌ β
β Compare with β
β Golden Signature β
β β β
β PASS/FAIL β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
Components
- LFSR: Generates pseudo-random test patterns
- Circuit Under Test: Your logic (via scan chains)
- MISR: Compresses outputs into signature
- Comparison: Match expected signature
LFSR - Pattern Generator
LFSR = Linear Feedback Shift Register
Generates pseudo-random sequence using XOR feedback.
module lfsr_4bit (
input clk, rst_n, en,
output reg [3:0] q
);
// Polynomial: x^4 + x^3 + 1
// Taps at positions 4 and 3
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= 4'b1111; // Non-zero seed required!
else if (en)
q <= {q[2:0], q[3] ^ q[2]}; // Shift + feedback
end
endmodule
LFSR Sequence
4-bit LFSR cycles through 15 values (2^4 - 1):
1111 β 0111 β 0011 β 0001 β 1000 β 0100 β
0010 β 1001 β 1100 β 0110 β 1011 β 0101 β
1010 β 1101 β 1110 β (back to 1111)
Never produces 0000 (would get stuck!)
MISR - Signature Analyzer
MISR = Multiple Input Signature Register
Compresses many outputs over many cycles into single signature.
module misr_4bit (
input clk, rst_n, en,
input [3:0] data_in,
output reg [3:0] sig
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sig <= 4'b0;
else if (en)
sig <= {sig[2:0], sig[3] ^ sig[2]} ^ data_in;
end
endmodule
How Signature Works
Cycle 1: Output = 1010 β MISR = 0x1A
Cycle 2: Output = 1100 β MISR = 0x3F
Cycle 3: Output = 0110 β MISR = 0x7B
...
Cycle N: Final Signature = 0xA5B7C3D1
If ANY cycle has wrong output β Signature changes!
Compare with expected: Match = PASS, Mismatch = FAIL
BIST vs External Test Comparison
| Aspect | External Test | BIST |
| Equipment | Expensive ATE | None needed |
| Test time | Limited by ATE | Can run long |
| Pattern storage | ATE memory | On-chip generation |
| Diagnosis | Detailed fail data | Usually pass/fail only |
| Field test | Not possible | Possible |
| Area overhead | None | 3-5% |
When to Use BIST
MBIST - Always!
Every embedded memory should have MBIST. It's:
- Standard practice
- Required by most customers
- Catches memory-specific defects
LBIST - Sometimes
Use for:
- Automotive (safety-critical)
- Medical devices
- High-reliability applications
- In-field testing
Summary
| Concept | Key Point |
| BIST | Chip tests itself |
| MBIST | Tests memories with March algorithm |
| LBIST | Tests logic with LFSR/MISR |
| LFSR | Generates pseudo-random patterns |
| MISR | Compresses outputs to signature |
| Benefit | No external tester, field testing |