πŸ”§ DFT Blog

Part 9 of 11

BIST - Built-In Self-Test

The chip that tests itself

By Praveen Kumar Vagala

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What is BIST?

BIST = Built-In Self-Test

Test logic embedded inside the chip. No expensive external tester needed.

Without BIST: With BIST: β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚External│────►│ Chip β”‚ β”‚ Chip β”‚ β”‚Tester │◄────│ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β””β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ BIST Engine β”‚ β”‚ $$$$$$ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ Expensive! β”‚ Self-contained! β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜

Two Types of BIST

TypeTestsUse Case
MBISTEmbedded memories (SRAM)Standard for all memories
LBISTRandom logicHigh-reliability applications

MBIST - Memory BIST

Architecture

β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ MBIST Controller β”‚ β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β”‚ β”‚ Address │───────────────┐ β”‚ β”‚ β”‚ Generator β”‚ β”‚ β”‚ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ β”‚ β–Ό β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β”‚ β”‚ Data │────────►│ β”‚ β”‚ β”‚ β”‚ Generator β”‚ β”‚ SRAM β”‚ β”‚ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ │────┐ β”‚ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β”‚ β”‚ β”‚ Expected β”‚ β”‚ β”‚ β”‚ β”‚ Data │───────┐ β”‚ β”‚ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ β”‚ β”‚ β–Ό β–Ό β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β”‚ β”‚ Comparator β”‚ β”‚ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”¬β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β”‚ β”‚ β”‚ β”‚ PASS/FAIL β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜

How It Works

  1. Address Generator: Cycles through all memory locations
  2. Data Generator: Creates test patterns (0s, 1s, checkerboard)
  3. Write to SRAM: Store test data
  4. Read from SRAM: Retrieve stored data
  5. Compare: Match expected vs actual
  6. Report: PASS if all match, FAIL otherwise

March Algorithm

Industry-standard memory test pattern.

March C- Algorithm

Step 1: ⇑(w0)      Write 0 to all locations, ascending
Step 2: ⇑(r0,w1)   Read 0, write 1, ascending  
Step 3: ⇑(r1,w0)   Read 1, write 0, ascending
Step 4: ⇓(r0,w1)   Read 0, write 1, descending
Step 5: ⇓(r1,w0)   Read 1, write 0, descending
Step 6: ⇓(r0)      Read 0, descending

Notation:
  ⇑ = Ascending address order
  ⇓ = Descending address order
  w0 = Write 0
  r1 = Read and expect 1

What March Catches

Fault TypeDescription
Stuck-atCell always 0 or 1
TransitionCell can't change
CouplingOne cell affects another
Address decoderWrong cell accessed
Read/Write logicData corruption

LBIST - Logic BIST

Tests random logic using pseudo-random patterns.

β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β”‚ β”‚ β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ β”‚ β”‚ LFSR │─────►│ │─────►│ MISR β”‚ β”‚ β”‚ β”‚(Patternβ”‚ β”‚ Circuit β”‚ β”‚(Signtr)β”‚ β”‚ β”‚ β”‚ Gen) β”‚ β”‚ Under Test β”‚ β”‚ β”‚ β”‚ β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β””β”€β”€β”€β”€β”¬β”€β”€β”€β”˜ β”‚ β”‚ β”‚ β”‚ β”‚ β–Ό β”‚ β”‚ Compare with β”‚ β”‚ Golden Signature β”‚ β”‚ β”‚ β”‚ β”‚ PASS/FAIL β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜

Components

  1. LFSR: Generates pseudo-random test patterns
  2. Circuit Under Test: Your logic (via scan chains)
  3. MISR: Compresses outputs into signature
  4. Comparison: Match expected signature

LFSR - Pattern Generator

LFSR = Linear Feedback Shift Register

Generates pseudo-random sequence using XOR feedback.

module lfsr_4bit (
    input            clk, rst_n, en,
    output reg [3:0] q
);
    // Polynomial: x^4 + x^3 + 1
    // Taps at positions 4 and 3
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= 4'b1111;  // Non-zero seed required!
        else if (en)
            q <= {q[2:0], q[3] ^ q[2]};  // Shift + feedback
    end
endmodule

LFSR Sequence

4-bit LFSR cycles through 15 values (2^4 - 1):

1111 β†’ 0111 β†’ 0011 β†’ 0001 β†’ 1000 β†’ 0100 β†’ 
0010 β†’ 1001 β†’ 1100 β†’ 0110 β†’ 1011 β†’ 0101 β†’ 
1010 β†’ 1101 β†’ 1110 β†’ (back to 1111)

Never produces 0000 (would get stuck!)

MISR - Signature Analyzer

MISR = Multiple Input Signature Register

Compresses many outputs over many cycles into single signature.

module misr_4bit (
    input            clk, rst_n, en,
    input      [3:0] data_in,
    output reg [3:0] sig
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            sig <= 4'b0;
        else if (en)
            sig <= {sig[2:0], sig[3] ^ sig[2]} ^ data_in;
    end
endmodule

How Signature Works

Cycle 1: Output = 1010 β†’ MISR = 0x1A
Cycle 2: Output = 1100 β†’ MISR = 0x3F
Cycle 3: Output = 0110 β†’ MISR = 0x7B
...
Cycle N: Final Signature = 0xA5B7C3D1

If ANY cycle has wrong output β†’ Signature changes!
Compare with expected: Match = PASS, Mismatch = FAIL

BIST vs External Test Comparison

AspectExternal TestBIST
EquipmentExpensive ATENone needed
Test timeLimited by ATECan run long
Pattern storageATE memoryOn-chip generation
DiagnosisDetailed fail dataUsually pass/fail only
Field testNot possiblePossible
Area overheadNone3-5%

When to Use BIST

MBIST - Always!

Every embedded memory should have MBIST. It's:

LBIST - Sometimes

Use for:

Summary

ConceptKey Point
BISTChip tests itself
MBISTTests memories with March algorithm
LBISTTests logic with LFSR/MISR
LFSRGenerates pseudo-random patterns
MISRCompresses outputs to signature
BenefitNo external tester, field testing