Part 8 of 11
At-Speed Testing
Catching defects that only appear at full speed
By Praveen Kumar Vagala
Why At-Speed?
Stuck-at tests are slow. They miss timing defects.
Stuck-At Test (Slow):
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Apply pattern, wait long time, check result
ā Plenty of time for signals to settle
At-Speed Test (Fast):
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ā ā
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Launch Capture (real chip speed!)
What At-Speed Catches
| Defect Type | Stuck-At | At-Speed |
|---|
| Hard shorts/opens | ā | ā |
| Weak transistors | ā | ā |
| Resistive defects | ā | ā |
| Path delay faults | ā | ā |
| Process variations | ā | ā |
Transition Fault Model
At-speed testing uses transition faults:
Slow-to-Rise (STR): Signal takes too long to go 0ā1
Slow-to-Fall (STF): Signal takes too long to go 1ā0
Expected | Actual (STR fault)
āāāāā | ā±āāāā
āāāā | āāāā±
Fast | Slow (misses clock!)
Two Launch Methods
LOC - Launch Off Capture
The capture clock launches the transition.
Waveform:
Load Pattern Launch Capture Unload
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CLK āāāāāāāā“āāāāāāāāāāāāāā“āāāāāāāāā“āāāāāāāāāāā“āāā
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At-speed gap
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Sequence:
- Shift in pattern (SE=1, slow clocks)
- Drop SE to 0
- Launch clock - Data starts transitioning through logic
- Capture clock - At-speed delay after launch
- Raise SE to 1
- Shift out captured response
LOS - Launch Off Shift
The last shift clock launches the transition.
Waveform:
Load Pattern Last Shift=Launch Capture
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CLK āāāāāāāā“āāāāāāāāāāāāāāāāāāā“āāāāāāāāāāāāāāā“āāā
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At-speed gap
SE āāāāāāāāāāāāāāāāāāāāāāāāāāā
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Sequence:
- Shift in pattern (SE=1)
- Last shift clock is the launch (transitions during shift)
- Drop SE
- Capture clock at-speed after launch
- Shift out
LOC vs LOS Comparison
| Aspect | LOC | LOS |
|---|
| Launch event | Dedicated capture clock | Last shift clock |
| SE during launch | Low | High (transitioning) |
| Clock control | Need fast switching | Shift clock at-speed |
| Transition coverage | Higher | Lower |
| Pattern count | Fewer | More |
| Timing complexity | More complex | Simpler |
| Industry usage | More common | Specific cases |
Detailed LOC Timing
Shift In Func. Shift Out
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CLK āāā¬āā¬āā¬āā¬āā¬āā¬āā¬āā¬āā¬āā¬āāāā¬āāāāā¬āāāā¬āā¬āā¬āā¬āā¬āā¬āā¬āā
1 2 3 4 5 6 7 8 9 10 L C 1 2 3 4 5 6 7
SE āāāāāāāāāāāāāāāāāāāāāāā āāāāāāāāāāāāāāāāā
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Slow shift clocks At Slow shift clocks
Speed
Key timing:
L = Launch clock
C = Capture clock
LāC gap = Target clock period (at-speed)
At-Speed Pattern Structure
Each at-speed pattern has two parts:
Pattern = Launch Pattern + Capture Pattern
Launch Pattern: Sets up initial state (value before transition)
Capture Pattern: Expected state after transition
Example testing STR (slow-to-rise) on node N:
Launch: N = 0 (initial state)
Capture: N = 1 (should transition to 1)
If chip is slow: N might still be 0 at capture ā FAIL!
At-Speed Timing Requirements
Launch-to-Capture Delay
Must be exactly one clock period (at target frequency).
Target: 1 GHz operation
Period: 1 ns
LāC delay must be exactly 1 ns (Ā± margin)
Clock Controller
Need on-chip or ATE clock control for fast switching:
Mode 1: Slow clocks for shifting (10 MHz)
Mode 2: Fast clocks for launch/capture (1 GHz)
Switch from slow ā fast ā slow within pattern
Coverage Improvement
At-speed adds significant value:
Typical coverage comparison:
Stuck-at only: 98% coverage ā 500 DPPM escapes
+ Transition: 95% coverage ā 100 DPPM escapes
DPPM = Defective Parts Per Million
Even 95% transition coverage catches defects that
99% stuck-at coverage misses!
Summary
| Concept | Key Point |
|---|
| Why at-speed | Catches timing defects |
| LOC | Launch from capture clock |
| LOS | Launch from last shift clock |
| Transition faults | Slow-to-rise, slow-to-fall |
| Key timing | Launch-to-capture = clock period |