Part 7 of 11

Scan Compression

Reducing test time from hours to minutes

By Praveen Kumar Vagala

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The Problem

Modern chips have millions of flip-flops. Testing without compression is impractical.

Example:
  Chip has:       10,000,000 flip-flops
  Shift in:       10M bits
  Shift out:      10M bits
  At 100MHz:      0.1 seconds per pattern
  With 10,000 patterns: 1000 seconds = 17 minutes per chip!
  
  At $0.01/second tester cost:
  17 minutes × $0.01/sec × 1M chips = $10M in test costs!

The Solution: Compression

Reduce the data volume between tester and chip.

Without Compression: ATE ──[10M bits]──► Chip ──[10M bits]──► ATE With 100:1 Compression: ATE ──[100K bits]──► Chip ──[100K bits]──► ATE 17 minutes → 10 seconds!

Compression Architecture

┌───────────────────────────────────────────────────────────────┐ │ │ │ ATE Chip ATE │ │ (10 ch) (10 ch)│ │ │ │ ┌────────┐ ┌─────────────────┐ ┌────────┐ │ │ ───►│ │────►│ │────►│ │───► │ │ ───►│ DEC │────►│ 1000 Scan │────►│ COMP │───► │ │ ───►│ OMP │────►│ Chains │────►│ ACT │───► │ │ ───►│ │────►│ │────►│ OR │───► │ │ └────────┘ └─────────────────┘ └────────┘ │ │ (expand) (compact) │ │ │ │ 10 channels → 1000 chains 1000 chains → 10 channels │ │ │ └───────────────────────────────────────────────────────────────┘

How Decompression Works

The decompressor expands few ATE channels to many internal scan chains using XOR networks.

ATE Input Channels:
  CH0, CH1, CH2, CH3, ... CH9 (10 channels)

Each scan chain gets a unique XOR combination:
  Chain[0]   = CH0 ⊕ CH2 ⊕ CH5
  Chain[1]   = CH1 ⊕ CH3 ⊕ CH7
  Chain[2]   = CH0 ⊕ CH4 ⊕ CH9
  Chain[3]   = CH2 ⊕ CH5 ⊕ CH8
  ...
  Chain[999] = CH1 ⊕ CH6 ⊕ CH7

Visual Representation

CH0 ─────────┬────────────┬──────────────► Chain 0 │ │ CH1 ────┬────┼────────XOR─┼──────────────► Chain 1 │ │ │ │ CH2 ────┼────┼──XOR───┘ └───XOR────────► Chain 2 │ │ │ │ │ └───┼─────────────┴─────────► Chain 3 │ │ └────────┴──XOR──────────────────► Chain 4

ATPG tool calculates what values to put on each ATE channel to achieve desired values on all chains.

How Compaction Works

The compactor compresses many scan chain outputs into few ATE channels using XOR trees.

Chain[0] ──────┬─────────────────────────────┐ │ │ Chain[1] ──XOR─┼───────────────┬─────────────┼──► CH0 │ │ │ Chain[2] ──────┴──XOR──────────┼───────────XOR──► CH1 │ │ Chain[3] ────────────┴─────────┼───────────────► CH2 │ Chain[4] ──────────────────────┴───────────────► CH3

Key insight: Any fault effect on any chain will propagate to at least one output.

Compression Trade-offs

X-Masking

Unknown values (X) in scan chains can corrupt compressed output.

Compression without X handling:
  Chain[0] = 1
  Chain[1] = X (unknown)
  Chain[2] = 0
  
  Compressed = 1 ⊕ X ⊕ 0 = X  ← Lost all information!

Solutions:

X-blocking: Mask out chains with X
X-bounding: Control X propagation
X-tolerant compactors

Masking

Some faults may "mask" each other through XOR.

If Chain[0] has fault effect = 1
And Chain[1] has fault effect = 1

Compressed = 1 ⊕ 1 = 0  ← Fault masked!

ATPG tools handle this by generating patterns carefully.

Compression Ratio

Compression Ratio = Internal Chains / ATE Channels

Example:
  1000 internal chains
  10 ATE channels
  Ratio = 100:1

Higher ratio = Faster testing, but harder ATPG
Lower ratio  = Easier ATPG, but slower testing

Typical: 50:1 to 200:1

Industry Compression Schemes

Vendor	Technology
Synopsys	DFTMAX, DFTMAX Ultra
Cadence	Modus
Mentor/Siemens	Tessent

All use similar principles: LFSR-based decompression, XOR compaction.

Benefits Summary

Metric	Without Compression	With 100:1 Compression
Test Data Volume	10 GB	100 MB
Test Time	17 min/chip	10 sec/chip
ATE Memory	Need huge memory	Fits in ATE
Cost per chip	$10	$0.10

Summary

Concept	Key Point
Problem	Too much data for millions of FFs
Decompressor	Expands few inputs to many chains (XOR)
Compactor	Reduces many outputs to few (XOR tree)
Ratio	Typically 50:1 to 200:1
Trade-off	X-handling, fault masking

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