πŸ”§ DFT Blog

Part 6 of 11

ATPG Basics

Automatic Test Pattern Generation explained

By Praveen Kumar Vagala

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What is ATPG?

ATPG = Automatic Test Pattern Generation

Software that automatically creates test patterns to detect manufacturing defects.

β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”Œβ”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β” β”‚ Netlist │─────►│ ATPG │─────►│ Patterns β”‚ β”‚ + Faults β”‚ β”‚ Tool β”‚ β”‚ (.stil) β”‚ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β””β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”€β”˜ β”‚ β–Ό Coverage Report

Fault Models

Stuck-At Faults (Primary Model)

Models a wire permanently stuck at logic 0 or 1.

Stuck-at-0 (SA0): Wire always 0, regardless of input Stuck-at-1 (SA1): Wire always 1, regardless of input Example: A ──┬── W ──► Buffer ──► Y β”‚ (SA0 fault on W) Good circuit: A=1 β†’ W=1 β†’ Y=1 Faulty: A=1 β†’ W=0 β†’ Y=0 ← Detectable!

Transition Faults (For Timing)

Models slow transistors that can't switch fast enough.

Slow-to-Rise (STR): 0β†’1 transition too slow Slow-to-Fall (STF): 1β†’0 transition too slow Expected Actual (STR) β”Œβ”€β”€β”€β”€ ╱──── β”€β”€β”€β”˜ ───╱ Fast rise Slow rise - may miss clock!

Other Fault Models

ModelCatches
Stuck-atOpens, shorts, manufacturing defects
TransitionWeak transistors, timing defects
Path DelayCritical path failures
BridgingShorts between adjacent wires
IDDQDefects causing excess current

How ATPG Works

For each fault, ATPG does three things:

1. Activate the Fault

Set conditions so good and faulty circuits produce different values.

To activate SA0 on wire W: - W must be 1 in good circuit - W is 0 in faulty circuit (stuck!) - Difference created!

2. Propagate to Output

Create a path from fault site to an observable output.

Fault β”‚ β–Ό Input ──AND── W ──AND── Output β”‚ C Set C=1 so W's value reaches Output (WΒ·1 = W)

3. Justify to Inputs

Work backwards to find required input values.

Need W=1 β”‚ A ──┬──AND──►W β”‚ B β”€β”€β”˜ To get W=1, need A=1 AND B=1

Complete Example

Detect SA0 on wire W: A ─────┬───AND───W───AND───Y β”‚ β”‚ B β”€β”€β”€β”€β”€β”˜ C β”€β”€β”€β”˜ Step 1 (Activate): Need W=1 in good circuit β†’ Set A=1, B=1 (W should be 1) Step 2 (Propagate): Need effect at Y β†’ Set C=1 (Y = WΒ·C = W) Step 3 (Justify): Already done! Test Pattern: A=1, B=1, C=1 Expected Y (good): 1Β·1Β·1 = 1 Expected Y (faulty): 0Β·1 = 0 ← Different! Fault detected!

Fault Classes

After ATPG runs, faults are classified:

ClassCodeMeaning
DetectedDTPattern exists to detect
Possibly DetectedPTMight detect (probabilistic)
UndetectedUDNo pattern found (yet)
ATPG UntestableAUStructurally impossible to test
UnobservableUOCan't see at any output
UncontrollableUCCan't set required value
TiedTITied to constant, not a fault
BlockedBLUser excluded from testing

Coverage Calculation

Fault Coverage = DT / (Total - AU - TI - BL) Γ— 100%

Example:
  Total faults:     1,000,000
  Detected (DT):      970,000
  Untestable (AU):     10,000
  Tied (TI):            5,000
  
  Coverage = 970,000 / (1,000,000 - 10,000 - 5,000)
           = 970,000 / 985,000
           = 98.5%

Fault Collapsing

Many faults are equivalent - one test detects multiple faults.

A ───┬─── W ───► Y β”‚ AND β”‚ B β”€β”€β”€β”˜ Equivalent faults (same test detects all): - A SA0 - B SA0 - W SA0 - Y SA0 Collapse 4 faults to 1 representative fault!

Benefits

ATPG Tool Flow (TetraMAX Example)

# 1. Read design
read_netlist design_scan.v
run_build_model

# 2. Read scan protocol
run_drc scan.spf

# 3. Set fault model
set_faults -model stuck
add_faults -all

# 4. Run ATPG
set_atpg -merge high
run_atpg -auto

# 5. Report coverage
report_faults -summary

# 6. Write patterns
write_patterns patterns.stil -format stil -replace

Summary

ConceptKey Point
ATPGAuto-generates test patterns
Stuck-atWire stuck at 0 or 1
TransitionSlow rising or falling edge
ActivateCreate difference at fault site
PropagatePath to observable output
JustifySet required input values
CoverageDT / (Total - AU)