What is Scan?

Scan connects all flip-flops into a long shift register, allowing direct access to internal state.

Normal Mode (Functional Operation)

Scan Mode (Test Operation)

Scan Flip-Flop Structure

A scan FF is a regular FF with a MUX added at the input:

Verilog Implementation

module scan_dff (
    input      clk,
    input      rst_n,
    input      d,           // Functional data
    input      si,          // Scan input
    input      se,          // Scan enable
    output reg q
);
    wire mux_out;
    
    // Scan MUX: SE selects between functional and scan data
    assign mux_out = se ? si : d;
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= 1'b0;
        else
            q <= mux_out;
    end
endmodule

Scan Test Operation

Step 1: Shift In (Load Pattern)

Step 2: Capture (Apply Test)

Step 3: Shift Out (Unload Response)

Complete Timing

Scan Chain Architecture

Real chips have multiple scan chains running in parallel:

Trade-offs

Scan DRC Rules

Design Rule Checks that MUST pass:

1. All FFs Must Be Scannable

Every flip-flop should be in a scan chain (unless specifically excluded).

2. Clocks Must Be Controllable

3. Async Resets Must Be Inactive

During scan shift:
  RST_N = 1 (inactive)
  
If RST_N = 0, all FFs reset - destroys scan data!

4. No Tri-State in Scan Path

5. No Combinational Loops