Part 4 of 11
Introduction to DFT
Why we need Design for Testability
By Praveen Kumar Vagala
The Problem
You've designed a chip with millions of flip-flops. How do you know each one works?
┌─────────────────────────────────────────┐
│ │
│ ┌───┐ ┌───┐ ┌───┐ │
│ │FF │────►│FF │────►│FF │ │
│ └───┘ └───┘ └───┘ │
│ ↑ Logic ↑ Logic ↑ │
│ │ │ │ │
│ Buried deep inside - can't access! │
│ │
└─────────────────────────────────────────┘
Without DFT:
- Can't directly set internal flip-flop values
- Can't directly observe internal flip-flop values
- Need complex functional patterns to test
- Low fault coverage
- Expensive testing
The Solution: DFT
DFT = Design for Testability
Add special circuitry to make testing easy.
┌─────────────────────────────────────────┐
│ │
│ SI──►┌───┐────►┌───┐────►┌───┐──►SO │
│ │SFF│ │SFF│ │SFF│ │
│ └───┘ └───┘ └───┘ │
│ │
│ All flip-flops connected in a chain! │
│ Can shift in any pattern, observe any │
│ value. │
│ │
└─────────────────────────────────────────┘
With DFT:
- Direct access to all flip-flops via scan chains
- Simple shift-capture-shift testing
- High fault coverage (>98%)
- Automated pattern generation (ATPG)
Key DFT Concepts
Controllability
How easy is it to set a node to 0 or 1?
Easy to control:
Input Pin ──► Node (directly connected)
Hard to control:
A ──┬──AND──┬──AND──┬──AND── Deep_Node
│ │ │
B ──┘ C ──┘ D ──┘
Need A=B=C=D=1 just to set Deep_Node=1!
Observability
How easy is it to see a node's value at outputs?
Easy to observe:
Node ──► Output Pin (directly connected)
Hard to observe:
Deep_Node ──AND──AND──AND── Output
(many gates to propagate through)
Testability = Controllability + Observability
DFT improves both by adding scan chains and test points.
Types of DFT
| Technique | What It Does |
|---|
| Scan | Connects all FFs into shift registers |
| ATPG | Auto-generates test patterns |
| BIST | Chip tests itself |
| JTAG | Standard debug/test interface |
| Compression | Reduces test data volume |
ASIC Design Flow with DFT
┌──────────────────────────────────────────┐
│ │
│ Specification │
│ │ │
│ ▼ │
│ RTL Design (Verilog) │
│ │ │
│ ▼ │
│ Synthesis ──► Gate-Level Netlist │
│ │ │
│ ▼ │
│ ┌─────────────────┐ │
│ │ DFT Insertion │ ← Scan chains added │
│ └────────┬────────┘ │
│ │ │
│ ▼ │
│ DFT Netlist + Scan Protocol │
│ │ │
│ ▼ │
│ ┌─────────────────┐ │
│ │ ATPG │ ← Patterns created │
│ └────────┬────────┘ │
│ │ │
│ ▼ │
│ Test Patterns (.stil) │
│ │ │
│ ▼ │
│ Place & Route │
│ │ │
│ ▼ │
│ Fabrication │
│ │ │
│ ▼ │
│ ┌─────────────────┐ │
│ │ ATE Testing │ ← Patterns applied │
│ └─────────────────┘ │
│ │
└──────────────────────────────────────────┘
Cost of Testing
Testing is expensive! Typically 30-50% of chip manufacturing cost.
| Factor | Impact |
|---|
| Test time | More patterns = more time = more cost |
| ATE equipment | $1M-10M per tester |
| Test escapes | Defective chip reaches customer = $$$$ |
DFT pays for itself by:
- Reducing test time (compression)
- Increasing coverage (fewer escapes)
- Enabling automated pattern generation
Summary
- DFT makes chips testable by adding scan chains
- Controllability = ability to set values
- Observability = ability to see values
- ATPG generates patterns automatically
- Goal: >98% fault coverage