The Big Picture

Step 1: RTL Design

Write clean, DFT-friendly RTL:

// Good practice: synchronous resets when possible
always @(posedge clk) begin
    if (sync_rst)
        count <= 0;
    else
        count <= count + 1;
end

// Avoid: tri-state buses internally
// Avoid: combinational loops
// Avoid: latches (unless intentional)

Step 2: Synthesis

Convert RTL to gate-level netlist.

# Example Synopsys DC script
read_verilog design.v
link
check_design

# Compile
compile_ultra

# Write netlist
write -format ddc -output design.ddc

Step 3: DFT Insertion

Add scan chains, BIST, JTAG to the netlist.

DFT Compiler Example (Synopsys)

# Read synthesized design
read_ddc design.ddc

# Define test clocks
create_clock -name clk -period 10 [get_ports clk]

# Configure scan
set_scan_configuration -chain_count 100
set_scan_configuration -clock_mixing no_mix

# Define test signals
set_dft_signal -view existing_dft -type ScanClock \
    -timing [list 45 55] -port clk

set_dft_signal -view existing_dft -type Reset \
    -active_state 0 -port rst_n

set_dft_signal -view existing_dft -type ScanEnable \
    -port scan_en -active_state 1

# Preview scan (check before insertion)
preview_dft

# Insert scan
insert_dft

# Check for violations
dft_drc

# Write outputs
write -format ddc -output design_scan.ddc
write_test_protocol -output scan.spf -test_mode all
write_scan_def -output scan.def

Key Outputs

Step 4: ATPG

Generate test patterns using the scan netlist.

TetraMAX Example (Synopsys)

# 1. Read design
read_netlist design_scan.v -library lib.db
run_build_model design

# 2. Read scan protocol
run_drc scan.spf

# 3. Add faults - Stuck-at
set_faults -model stuck
add_faults -all

# 4. Run ATPG
set_atpg -merge high -verbose
run_atpg -auto

# 5. Report
report_faults -summary > coverage_stuck.rpt
report_faults -class ud -limit 100 > undetected.rpt

# 6. Transition faults
set_faults -model transition -fault_coverage
add_faults -all
run_atpg -auto

report_faults -summary > coverage_trans.rpt

# 7. Write patterns
write_patterns patterns.stil -format stil -replace
write_faults faults.gz -compressed -replace

Step 5: Verify Patterns

Simulate patterns on gate-level netlist.

# Run pattern simulation
run_simulation -patterns patterns.stil

# Check for mismatches
report_simulation_failures

Reading Coverage Reports

Sample Report

========================================
       FAULT COVERAGE SUMMARY
========================================
Test Mode:          Internal_scan
Fault Model:        Stuck-at

                    #Faults    Coverage
                   ---------  ---------
DT (Detected)        985,234     98.52%
PT (Possibly Det.)     2,156      0.22%
AU (ATPG Untest.)      8,543      -----
UD (Undetected)        4,067      0.41%
TI (Tied)              3,421      -----
                   ---------
Total               1,003,421

Fault Coverage:        98.52%
Test Coverage:         99.37%
Patterns:              15,234
CPU Time:              2h 15m
========================================

Key Metrics

Debugging Low Coverage

Step 1: Check DRC Violations

report_drc > drc.rpt

Common issues:

• Clocks not controllable
• Resets not controllable
• FFs not in scan chain

Step 2: Analyze Undetected Faults

report_faults -class ud > ud_faults.rpt

Look for patterns:

• All in same module? → Design issue
• All on same signal type? → Constraint issue
• Mostly unobservable? → Need test points

Step 3: Fix Issues

DFT Checklist

Before signoff:

□ All FFs in scan chains
□ No DRC violations
□ Stuck-at coverage > 98%
□ Transition coverage > 95%
□ No simulation mismatches
□ MBIST for all memories
□ JTAG present and verified
□ Compression working
□ At-speed tests included
□ Pattern count acceptable

File Formats

Common Tools by Vendor