Setup time, hold time, and why your chip might fail
A logic design that's functionally correct can still fail if timing is wrong.
Timing violations cause:
| Parameter | Symbol | Description |
|---|---|---|
| Setup Time | Tsu | Data must be stable BEFORE clock edge |
| Hold Time | Th | Data must be stable AFTER clock edge |
| Clock-to-Q | Tcq | Time for output to change after clock |
| Clock Period | Tclk | Time between clock edges |
Data arrives TOO LATE - after the setup window.
For data to arrive on time:
Tcq + Tcomb < Tclk - Tsetup
Where:
Tcq = Clock-to-Q of source FF
Tcomb = Combinational logic delay
Tclk = Clock period
Tsetup = Setup time of destination FF
Example:
Tcq = 0.2ns, Tcomb = 3ns, Tsetup = 0.1ns
Tclk must be > 0.2 + 3 + 0.1 = 3.3ns
Max frequency = 1/3.3ns = 303 MHzData changes TOO FAST - before hold window ends.
For hold to be met:
Tcq + Tcomb > Thold
Where:
Tcq = Clock-to-Q of source FF (min)
Tcomb = Combinational logic delay (min)
Thold = Hold time of destination FF
If data arrives too fast, add delay buffers!The longest path determines maximum clock frequency.
Static Timing Analysis (STA) tools find critical paths:
Path 1: FF_A → AND → OR → MUX → FF_B = 2.5ns
Path 2: FF_A → BUF → FF_B = 0.5ns ← Fast (not critical)
Path 3: FF_C → ADDER → FF_D = 4.2ns ← CRITICAL PATH!
Max frequency = 1 / (4.2ns + Tsetup) = ~230 MHzClock arrives at different times to different flip-flops.
Destination clock is delayed. Helps setup, hurts hold.
Setup equation with skew:
Tcq + Tcomb < Tclk - Tsetup + Tskew ← Easier to meet!
Hold equation with skew:
Tcq + Tcomb > Thold + Tskew ← Harder to meet!Destination clock arrives early. Hurts setup, helps hold.
Variation in clock edge timing from cycle to cycle.
Jitter reduces timing margin. Must be accounted for in timing analysis.
FF → Combinational Logic → FF
Most common path. Constrained by clock period.Input Pin → Logic → FF
Constrained by input delay constraint.FF → Logic → Output Pin
Constrained by output delay constraint.| Solution | How |
|---|---|
| Reduce clock frequency | Increase clock period |
| Pipeline | Add FF stages to break long paths |
| Use faster cells | Low-Vt cells (more power) |
| Optimize logic | Reduce gate count |
| Better placement | Reduce wire delay |
| Solution | How |
|---|---|
| Add delay buffers | Insert buffers in path |
| Use slower cells | High-Vt cells |
| Increase wire length | Route longer path |
Startpoint: reg_a (rising edge-triggered flip-flop)
Endpoint: reg_b (rising edge-triggered flip-flop)
Path Group: clk
Path Type: max (setup check)
Point Incr Path
---------------------------------------------
clock clk (rise edge) 0.00 0.00
reg_a/CK (rising edge) 0.05 0.05
reg_a/Q (Tcq) 0.15 0.20
U1/Y (AND2) 0.10 0.30
U2/Y (OR2) 0.12 0.42
U3/Y (MUX2) 0.18 0.60
reg_b/D (setup) 0.08 0.68
data arrival time 0.68
clock clk (rise edge) 1.00 1.00
reg_b/CK (clock path) 0.05 1.05
library setup time -0.08 0.97
data required time 0.97
slack (MET) 0.29 ← Positive = GOOD!| Concept | Key Point |
|---|---|
| Setup Time | Data stable BEFORE clock |
| Hold Time | Data stable AFTER clock |
| Tcq | Delay from clock to output |
| Critical Path | Longest path = max frequency limit |
| Clock Skew | Clock arrives at different times |
| Slack | Positive = good, Negative = violation |